Observable differences in the time domain measurements were lower peak magnitudes and more dampening in the parasitic ringing of the substrate noise. Another technique that is commonly used to reduce substrate noise is through the application of guard rings. For this part of the experiment, the effectiveness of a die perimeter ring and a guard ring were explored. In the nominal case previous measurements both rings were left floating. The die perimeter ring is a ring that surrounds the periphery of the chip. Multi-user context inference based on neural networks The large effective area of this ring reduces the impedance between the substrate and ground. The guard ring, on the other hand, simply encloses all of the PRNGs. Its close proximity to the noise source provides a shunt path for noise currents injected into the substrate. the changes in the RMS voltages of the measured substrate noise when the die perimeter ring is grounded, when the guard ring is grounded, and when both are grounded. Multi-user context inference based on neural networks As seen in this figure, a grounded guard ring reduces the substrate noise slightly more than the die perimeter ring. In general, a combination of both shows more improvement than either alone. MICROPROCESSOR CORES Although the PRNG blocks are useful to analyze the differences in the substrate noise injected by a synchronous and an asynchronous circuit, these blocks are in general not a goo measure of the substrate noise that would be present in a typical mixed-signal chip. A more practical comparison in terms Die photograph of the synchronous CBL and asynchronous NCL The die area of the respectively. of substrate noise can be found with a microprocessor. Multi-user context inference based on neural networks Microprocessors are commonly incorporated onto large mixed-signal chips as application specific functional blocks. In order to extend this analysis, another test chip was fabricated with a synchronous and an asynchronous version of a generic microprocessor. The die photo of the test chip is This chip was fabricated in a heavily-doped process and packaged in a. The respective die areas for the two microprocessor cores for the NCL. Aside from the two microprocessor cores, the designs share a program memory, Multi-user context inference based on neural networks a data memory, and an external memory interface for reading and writing from an off-chip source. The common components of the design are physically placed between the two cores to maintain layout symmetry for substrate noise comparisons between the CBL and NCL designs pins and peripherals have also been kept to a bare minimum to maintain the integrity of the substrate noise analysis. For this portion of the experiment, the processors are loaded with a software equivalent of the pseudo random number algorithm used in the PRNGs. The is clocked at to obtain the equivalent operating speed of the NCL show the measured substrate noise from the two processors in the time and the frequency domains, respectively. Multi-user context inference based on neural networks From these measurements, the RMS substrate noise generated by the asynchronous design was found to be less than that generated by the synchronous design. As seen in these plots, the noisewaveforms and their corresponding spectra exhibit similar characteristics to those seen in the PRNG measurements. However, there are a number of additional features here that cannot be solely attributed to the noise mechanisms of synchronous and asynchronous circuits that were discussed earlier. Multi-user context inference based on neural networks Multi-user context inference based on neural networks In this section, further analysis of these measurements will demonstrate how the substrate noise from larger, more complex digital blocks also reflects the architectural implementation of the digital block and the software or algorithm that is used.