A networking perspective on self-organizing intersection management
Architectural Contribution to Substrate Noise Considering the numerous types of possible implementations for any given architecture, it would be very difficult to simply generalize the contribution of the architecture to the injected substrate noise. However, from a purely system level point of view, many large digital blocks A networking perspective on self-organizing intersection management tend to exhibit similar high level structures and flow of operation the main system-level blocks for the microprocessor are: the arithmetic logic unit ALU, the datapath, the register file, and the RAM.
Although the substrate noise from any one of these blocks is not any more unique than the others, the order and timing of their operation creates noticeable frequency components in the substrate noise spectrum. This contribution can readily be seen where the frequency axis has been expand A networking perspective on self-organizing intersection management ed to show more resolution in the noise spectra from the. In the synchronous implementation, each instruction cycle is four clock cycles long. Since the processor will be performing similar tasks for each p A networking perspective on self-organizing intersection management ortion of this instruction cycle, a strong frequency component can be seen at a quarter of the clock frequency and its harmonics.
A networking perspective on self-organizing intersection managements
In the time domain, this instruction cycle is visible as slightly larger spikes A networking perspective on self-organizing intersection management for every fourth clock edge. Another architecture induced feature that is noticeable in the measurements are the memory accesses in the RAM. From the time-domain plot in the two large noise spikes seen in this portion of the measurement were determined to be caused by memory accesses. An expanded look at the time axis shows that these large spikes coincide with the instruction fetches from the RAM. Recall that the two cores share a common block of memory. The reason the RAM was not implemented separately for the is because of the combinational nature of the memory circuit. Due to the relatively large size of the RAM itself compared to the it can be seen that the effect of thememory accesses are very pronounced in the substrate noise measurement. In fact, from the magnitude of these spikes, the RAM is the dominant noise source for. A networking perspective on self-organizing intersection management The presence of this larger, more synchronized source of noise in the reflects the smaller improvement seen in this experiment comparedto the PRNG case.
For the CBL, the corresponding memory accesses are embedded in the synchronous A networking perspective on self-organizing intersection management switchingof the microprocessor so it is not as discernable from the measurement.Software Contribution to Substrate Noise The second component of substrate noise that is often present in large digital blocks is the component caused by the software or the algorithm. Whereas the architectural contribution to the substrate noise will be present regardless of the function of the, the contribution due to software is more instantaneous in nature. The software induced noise for this experiment can be recognized by noticing that the PRNG program loaded in each processor is instruction cycles long. As the program is looping through this section of code, there will be an additional frequency component equivalent to the total run time of the loop. A networking perspective on self-organizing intersection management This is seen in both the CBL and NCL spectra as small tones at and its harmonics. In order to verify that these tones are due to the software loop, the CBL and were loaded with an equivalent PRNG algorithm where the loop length is determined by the output of the pseudo-random sequence. shows the spectrum of the measured substrate noise using this program.