As seen in the schematic, one input is capacitively coupled to the substrate with a MOS capacitor while the other input is capacitively coupled to a dedicated ground pin. The differential output is then buffered with a source follower to drive a load. On-chip probing is used to minimize any measurement parasitics. In our first experiment, CBL and NCL versions of an linear congruential pseudo-random number generator PRNG were implemented in a heavily-doped process. A block diagram of this circuit is As seen in the figure, this algorithm is a simple modulo arithmetic operation Linear congruential random number generator. A hierarchical mobility management scheme for content-centric networking Switching distribution for the top synchronous and bottom asynchronous PRNGs. Number of transitions normalized to total number of gates in each block. consisting of a multiplier, an adder, and a register. The purpose of this PRNG is simply to emulate random switching noise in the substrate so the proper seed value was selected to generate a sequence of data values. the switching distribution from a gate-level simulation of the CBL and NCL PRNGs. Since the number and type of gates in the two designs are different, the number of output switching transitions in each design is normalized to the total of number of gates in the block for a comparative figure of merit. A hierarchical mobility management scheme for content-centric networking The CBL clock for this simulation is approximately.As seen in the figure, all of the switching activity occurs right after the rising edge of the clock. The transitions in each cycle are spread in a pulse-like distribution due to finite gate delay. At the peak of this distribution, nearly half of the gates in the design are making a transition. In contrast, the switching for the asynchronous design is quite evenly spread in time.Note that slightly higher switching activity is seen at approximate intervals of. These spikes correspond to the switching of the NCL output registers. The frequency at which these occur appear to be about twice the rate of the CBL clock, but these additional spikes are actually due to the return-to-zero or transition to NULL state behavior of the NCL logic.The die photograph of the chip with the PRNGs is shown in In order to ensure that the substrate noise from the CBL photograph of the synchronous CBL and asynchronous NCL pseudo-random number generators PRNG. The effective die areas are and, respectively. Sense amplifier is labeled SA in die photo. A hierarchical mobility management scheme for content-centric networking and NCL PRNGs is observable in the measurements, a total were placed on the die. The effective die areas were for the CBL block for the NCL block. Rows of the synchronous and asynchronous PRNGs were inter-digitated on the die to provideequivalent distance to the sensing circuits. In this section, the substrate noise from the CBL and NCL PRNGs are compared when the die is packaged in a package and when it is mounted directly on the PCB as a chip-on-board package. The package represents a high inductance package that will augment the inductive effectsof the supply noise and switching noise from the digital block. The chip-on-board package is a low inductance package that minimizes the contribution from the aforementioned source of noise. Comparing and contrasting the experimental results from these two packages allows conclusions to be drawn from the effect of asynchronous blocks versus their synchronous counterpart. A hierarchical mobility management scheme for content-centric networking First, an overview of the experimental results will be shown.