VANET via Named Data Networking

VANET via Named Data Networking

the substrate noise generated by a synchronous and an equivalent asynchronous implementation of a simple function are compared and analyzed.Next, the analysis is expanded to examine the noise from a typical large digital block such as a synchronous CBL processor and an asynchronous NCL processor. In order to gauge the practical impact of the substrate noise on an analog block, the performance degradation of a delta-sigma modulator DSM is evaluated in the presence of the substrate noise from each processor. VANET via Named Data Networking These measurements provide insight into noise tolerant analog/RF circuit design techniques. CBL is currently the most popular type of logic architecture for digital circuits. For this type of architecture, a signal in the form of a clock is used to control data transfer between Boolean logic gates and flip-flops.

In many cases, the clock is a global signal that synchronizes all of the switching in the design, hence the name synchronous logic. However, as mentioned above, the clock signal is considered a major noise contributor from a substrate noise point of view.NCL designs circumvent this problem by completely eliminating the clock. VANET via Named Data Networking Instead, this delay-insensitive form of logicuses a handshaking protocol to propagate data. For example,once some block has completed an operation, an acknowledgement signal along with the data is sent to the next block. VANET via Named Data Networking The second block uses the data for its own operation and upon completion, sends an acknowledgment back. At this point, the first block voids the data and moves on to its next task. As expected, the lack of synchronization gives an NCL circuit a distinct advantage with respect to switching noise and supply noise.

VANET via Named Data Networkings

Both of these noise mechanisms are much lower for asynchronous circuits because uncorrelated switching means that the peak currents injected into the substrate are much lower at any given time. Power consumption is also slightly lower for NCLdesigns. VANET via Named Data Networking Intuitively, it may seem that the opposite is true since NCL gates need to complete a handshaking protocol for each equivalent CBL clock edge. However, it turns out that on average, the power consumption tends to be lower because NCL designs do not have to deal with any additional clock driving circuitry and because only relevant portions of the circuit are active at any given time to resolve mobility management in named data networking. One disadvantage with NCL circuits is that NCL designs are typically larger than their Boolean counterpart. The reason for this difference in size is because NCL gates have to maintain the additional overhead for holding state information The goal for this experiment is to measure the substrate noise from a synchronous block and an asynchronous block to determine which is noisier.

In order to achieve this goal, functionally identical CBL and NCL designs are placed on a chip and used as noise generators. The two designs have separate power rails in order to measure the substrate noise generated for each. For a fair comparison, the CBL block is clocked approximately at the equivalent operating speed of the NCL block. The equivalent operating speed is defined as the CBL clock frequency for which the total completion time of a given task or program is about the same for both designs. VANET via Named Data Networking With either the CBL or NCL circuit on, a sensing circuit is placed equidistance from the two blocks to measure the noise in the substrate. VANET via Named Data Networking A schematic of the sensing circuit is shown in This design is based on that from The simple differential pair has close to unity gain along with a very wide bandwidth for broadband noise measurements.