Automatic control on transmission power in wireless networking

Automatic control on transmission power in wireless networking

Most of these methods attempt to reduce noise coupling by either blocking or actively canceling the noise in the substrate An alternative approach is to reduce the amount of noise that is injected from the digital block For a typical clocked Boolean logic CBL design, the main sources of noise injection are the clock tree and synchronous switching. The clock tree, used to distribute the clock across the chip, represents a large capacitive load in terms of both power and noise generation. Synchronous switching noise is the result of thousands of digital gates switching relatively close in time.

Since the inductive portion of the noise coupling is heavily dependent on the time derivative of the supply current , these two noise sources are further magnified due to the current switching nature of conventional CMOS CBL designs. Automatic control on transmission power in wireless networking As a result, a number of new constant current logic families such as current-steering logic and current-balanced logic were proposed to reduce substrate noise. However, it was shown that the improvement offered, if any, from these two types of logic only occur when the inductive coupling portion was dominant For small, lowinductance packages, the improvement over CMOS was negligible since the capacitive coupling portion is now dominant . Another technique to reduce the noise from the digital blocks is minimizing by spreading the transitions in time.

Automatic control on transmission power in wireless networkings

As mentioned above, synchronous switching causes a large number of digital gates to switch relatively close in time. Automatic control on transmission power in wireless networking Since all of this occurs in a relatively short time period, the effect of the injected noise tends to accumulate. When a global clock event occurs, the majority of the CBL transitions are concentrated around the same time, resulting in large noise. One possible approach is to intentionally skew the clock signal that is distributed to various domains on the chip. Although considerable improvement has been shown with this technique, there are practical limits on the extent of the skew and on the number of clock regions that are attainable. Even with an optimized solution, the switching is still fundamentally synchronized and the clock tree still presents itself as a major source of noise. Further improvement can be made if the transitions are somehow more evenly spread in time.

This can be made possible with a fully asynchronous design approach. LE EXPERIMENTAL CHARACTERIZATION AND ANALYSIS OF AN ASYNCHRONOUS APPROACH With a clockless logic, data is assessed and propagated independently by each gate. Automatic control on transmission power in wireless networking Thus, switching is localized, and forthe most part, independent of activity elsewhere on the chip. Compared to the synchronous approaches, an asynchronous solution should inject less substrate noise because spreading out the transitions both reduces the inductive portion and disperses the accumulation effect of the capacitive component. A number of studies have demonstrated that asynchronous circuits have tremendous power and noise savings over their synchronous counterparts Prior work on the asynchronous implementation has shown that the supply current peaks and the corresponding emission spectrum of the asynchronous approaches is much lower than the synchronous counterpart.

The focus of this paper is on an evaluation of the noise injected into the silicon substrate and its propagation to sensitive analog circuitry for both asynchronous and synchronous circuits. As there are many different asynchronous design styles available, it would be difficult to provide a fair and comprehensive study of how the power and noise savings of asynchronous circuits translates to reduced noise injected into the substrate. As a result, this work has examined one representative type of asynchronous logic called NULL convention logic In this paper, Automatic control on transmission power in wireless networking